In MOS dynamic random access memories (DRAMs), one of the failures that is difficult to detect is defects in the dielectric between the gates of transistors and the substrate. This dielectric has most often been silicon oxide but is also other materials or combinations of materials. One gate dielectric that is used comprises a first layer of oxide on the substrate, a nitride layer on the first oxide layer, then a second oxide layer. This combination is often referred to as ONO. This dielectric is quite thin. Defects in it may be marginal and not result in a failure until after some usage. These types of defects have resulted in testing difficulties. The most widely used approach has been to accelerate the manifestation of these defects with a period of high temperature burn-in. Burn-in takes quite some time and is a costly part of the testing process. It has been recognized that another approach to accelerated testing is to use higher voltages to stress dielectrics. Some of the advantages of this approach are pointed out in U.S. Pat. No. 4,465,973, Countryman, Jr. That patent described a technique for applying a stress voltage to one of the plates of the capacitor in DRAM. One common way of making a DRAM is to have all of the capacitors have one terminal formed in a common sheet of polysilicon. Applying a stress voltage to this common electrode is useful for testing the dielectric between this common polysilicon layer and the substrate and the dielectric between this common polysilicon layer and an overlying second polysilicon layer.
Another test that is needed, however, is to test the dielectric between the second layer of polysilicon and the substrate. For each memory cell in a DRAM, there is a capacitor and a transistor coupled together. The transistor is used for transferring charge to and from the capacitor and is often referred to as the transfer device. For the case in which the first polysilicon layer is used for a common plate for the capacitors in the array, the second layer of polysilicon is used for the gates of these transfer devices. There is then a gate dielectric which is quite thin between the second layer of polysilicon and the substrate. This gate dielectric is also susceptible of having defects which do not immediately manifest a failure so that burn-in is generally required to discover these defects.